FIG. 1 (Prior Art) is a block diagram of a type of direct current to direct current (DC-DC) converter 1 called a buck converter. There are several types of buck converters, but the example illustrated includes a synchronous pulse width modulation controller 2, a P-channel field effect transistor 3 (PFET), an N-channel field effect transistor 4 (NFET), an inductor 5, and a capacitor 6. Controller 2 controls the PFET and NFET such that only one of the two switches is conductive at a time. If PFET 3 is conductive, then supply voltage VIN is coupled to node 7 and the current in inductor 5 rises linearly. When NFET 4 is conductive, node 7 is coupled to PGND (ground) and the current in inductor 5 decreases linearly.
FIG. 2 (Prior Art) is a diagram that illustrates current flow in inductor 5. The average inductor current IAVE is indicated by line 8. As is well understood in the art, the output voltage VOUT across load 10 is approximately equal to the supply voltage VIN multiplied by the duty cycle (conductive time versus nonconductive time) of the high side switch PFET 3. Controller 2 monitors VOUT via its feedback (FB) input terminal 9 and controls the duty cycle of PFET 3 such that IAVE delivered to load 10 causes the voltage VOUT to be regulated to the desired voltage.
FIG. 3 (Prior Art) is an example of a conventional integrated circuit 11 that is available on the market to realize a buck converter. Dashed line 12 represents the edge of the integrated circuit. To use integrated circuit 11, the terminal 13 (L) is coupled to a first terminal of an external inductor as in the example of FIG. 1. The second terminal of the external inductor is coupled to the feedback input terminal 14 as in the example of FIG. 1. The second terminal of the inductor is coupled to a load. A capacitor is connected between the second terminal of the inductor and ground potential as in the example of FIG. 1. The specific buck converter integrated circuit 11 of FIG. 3, however, also has other terminals and functionalities. For example, the buck converter can be disabled by placing an appropriate digital value on an EN input terminal 15. The switching of the PFET and NFET can be made synchronous to an external clock signal. If a digital clock signal is provided on an input terminal 16 (SYNC), then this clock signal is used to synchronize the switching of the PFET and NFET. If, however, there is no clock signal present on SYNC terminal 16, then a clock signal generated on the integrated circuit 11 is used as a time base to switch the PFET and NFET. If the integrated circuit 11 determines that it is regulating the output voltage across the load in an acceptable fashion, then it asserts a digital one-bit signal on an output terminal 17 (PG). If the integrated circuit 11 determines that it is not regulating the output voltage in this acceptable fashion, then integrated circuit 11 deasserts the digital one-bit signal on the PG output terminal 17. The integrated circuit 11 may be made to drive the load to have one of two maximum current limit values. If a digital value on input terminal 18 (ILIM) is set to a first digital logic value, then the first predetermined current limit is used, otherwise if the digital value on input terminal ILIM 18 is set to a second digital logic value, then the second predetermined current limit is used. An external capacitor is to be coupled to terminal 19 (FC) so that the supply voltage for the undervoltage lockout bias supply circuit is a filtered voltage.
The integrated circuit 11 can be used in many different applications by configuring its various inputs and using its various outputs appropriately. For additional details, see the SLVS294D datasheet, September 2000, revised March 2006, for the TPS62000 family of DC-DC converters available from Texas Instruments of Dallas, Tex.
FIG. 4 (Prior Art) is a perspective view of the versatile buck converter integrated circuit 11 of FIG. 3. Rather than the semiconductor die being packaged in an integrated circuit package with leads, the upper surface of the die is provided with twelve microbumps 20. Each microbump is one terminal. Die 12 is then surface mounted directly to a printed circuit board, such that the microbumps 20 on the face side of die 12 are soldered directly to corresponding pads on the printed circuit board. A die provided with microbumps in this fashion is said to be a “chip scale packaged” or in a “chip scale package” (CSP).
FIG. 5 (Prior Art) is a table illustrating a correspondence between the terminals of integrated circuit die 12 and the functions of the various terminals. A terminal in the table of FIG. 5 is identified by its location on the face side of die 12. As can be seen from FIG. 4, there are three rows of microbumps where each row includes four microbumps. There are four columns of microbumps. FIG. 6 (Prior Art) indicates the row and column numbering convention used in the table of FIG. 5. Although the architecture of the integrated circuit 11 of FIGS. 3-6 works well in many applications and allows the integrated circuit 11 to be used in many applications, an improved architecture is desired.